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1 features ? reference oscillator up to 15 mhz (tuned) oscillator buffer output (for am up/down conversion) two programmable 16-bit dividers fine-tuning steps possible fast response time due to integrated loop push-pull stage 3-wire bus (enable, clock and data; 3 v and 5 v microcontrollers acceptable) four programmable switching outputs (open drain) three dacs for software controlled tuner alignment low-power consumption high s/n ratio integrated band gap ? only one supply voltage necessary description the U4256BM-r is a synthesizer ic for fm receivers and an am up-convertion system in bicmos technology. together with the am/fm ic t4258 or u4255bm, it performs a complete am/fm car radio front-end, which is recommended also for rds (radio data system) applications. it is controlled by a 3-wire bus and also contains switches and digital to analog converters (dacs) for software-controlled alignment of the am/fm tuner. the U4256BM-r is the pin-compatible succesor ic of U4256BM-n. pin configuration figure 1. pinning sso20 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 en data clk swo1 swo2 swo3 swo4 gndan oscout oscin mx2lo vs pd pdo dac2 v5 9 11 12 fmoscin dac1 gnd 10 dac3 U4256BM-r frequency synthesizer for radio tuning U4256BM-r preliminary rev. 4562b?audr?02/03
2 U4256BM-r 4562b?audr?02/03 figure 2. block diagram pin description pin symbol function 1 pdo phase detector output 2 pd pulsed current output 3 dac1 digital-to-analog converter 1 4 dac2 digital-to-analog converter 2 5 dac3 digital-to-analog converter 3 6 vs supply voltage analog part 7 swo1 switching output 1 8 swo2 switching output 2 9 swo3 switching output 3 10 swo4 switching output 4 11 gnd ground, digital part 12 oscout reference oscillator output 13 oscin reference oscillator input 14 v5 capacitor band gap 15 mx2lo oscillator buffer output 16 data data input 17 clk clock 18 en enable 19 fmoscin fm-oscillator input 20 gndan ground, analog part fm- preamp n- divider phase detector current sources dac1 am/fm dac2 dac3 3-bit v ref swo1 swo2 swo3 swo4 switching outputs r- divider oscillator osc buffer 3w- bus interface 16 17 18 13 12 15 19 7 8 9 10 oscin oscout mx2lo clk data en fmoscin 6 1 2 5 4 3 v ref 14 11 20 gndan v5 gnd dac3 dac2 dac1 vs pdo pd tuning dac bandgap
3 U4256BM-r 4562b?audr?02/03 functional description for a tuned fm-broadcast receiver, the following parts are needed: voltage-controlled oscillator (vco) antenna amplifier tuned circuit rf amplifier tuned circuit typical modern receivers with electronic tuning are tuned to the desired fm frequency by the frequency synthesizer ic U4256BM-r. the special design allows the user to build software-controlled tuner alignment systems. two programmable dacs (digital-to- analog converter) support the computer-controlled alignment. the output of the pll is a tuning voltage which is connected to the vco of the receiver ic. the output of the vco is equal to the desired station frequency plus the if (10.7 mhz). the rf and the oscillator signal (vco) are both input to the mixer that translates the desired fm chan- nel signal to the fixed if signal. for fm, the double-conversion system of the receiver requires exactly 10.7 mhz for the first if frequency, which determines the center fre- quency of the software-controlled integrated second if filter. if this oscillator tuning feature is not used, the internal capacities have to be switched off and the oscillator has to be operated with high-quality external capacities to ensure that the operational frequency is exactly 10.250 mhz. when dimensioning the oscillator circuit, it is important that the additional capacities enable the oscillator to operate through its complete tracking range. the oscillating abil- ity depends very strongly on the used crystal oscillator. initializing the oscillator should be established without switching any additional capacities to guarantee that the oscilla- tor starts to operate properly. due to the lower quality of the integrated capacities compared to discrete capacities, the amount of the switched integrated capacities should always be minimized. (if necessary reduce tracking range or use another crystal oscillator.) the U4256BM-r has a very fast response time of maximum 800 s (at 2 ma, f step = 50 khz, measured on mpx signal). it performs a high signal to noise ratio. only one supply voltage is necessary, due to a integrated band gap. input/output interface circuits pdo (pin 1) pdo is the buffer amplifier output of the pll. the bipolar output stage is a rail-to-rail amplifier. pd (pin 2) pd is the current charge pump output of the pll. the current can be controlled by setting the bits. the loop filter has to be designed corresponding to the choosen pump current and the internal reference frequency. a recommendation can be found in the application circuit. the charge-pump current can be choosen by setting the bits 71 and 70 as following: ipd (a) b71 b70 25 0 0 100 0 1 500 1 0 2000 1 1
4 U4256BM-r 4562b?audr?02/03 figure 3. internal components at pdo connection fmoscin (pin 19) fmoscin is the preamplifier input for the fm oscillator signal. figure 4. internal components at fmoscin mx2lo (pin 15) mx2lo is the buffered output of the crystal oscillator. this signal can be used as a refer- ence frequency for u4255bm or t4258. the oscillator buffer output can be switched by the oscb bit as following (bit 69) figure 5. internal components at mx2lo pd v s v s v s pdo fmoscin v 5 mx2lo ac voltage b69 on 0 off 1 v5 v5 oscin mx2lo
5 U4256BM-r 4562b?audr?02/03 function of dac1, 2 in fm and am mode (pin 3 and pin 4) for automatic tuner alignment, the dac1 and dac2 of the U4256BM-r can be con- trolled by setting gain of vpdo and offset values. the following figure shows the principle of the operation. in fm mode the gain is in the range of 0.69 v (pdo) to 2.16 v (pdo) . the offset range is +0.56 v to -0.59 v. for alignment, dac1 and dac2 are con- nected to the varicaps of the preselection filters. for alignment, offset and gain is set for having the best tuner tracking. figure 6. principle operation for alignment the dac mode can be controlled by setting the bit 34 as following: if bit 34 = 1 (am mode), the dac1, dac2 can be used as standard dac converters. the internal voltage of 3 v is connected to the gain- and offset-input of dac1 and dac2 (only in am mode). the gain is in the range of 0.46 3 v to 3.03 3 v. the offset range is +1.46 v to -1.49 v. figure 7. internal components at dac1,2 output dac mode b34 fm 0 am 1 pdo (fm) offset dac1,2 +/- gain vref (am) (3 v) bit 34 vs dac1,2
6 U4256BM-r 4562b?audr?02/03 dac 1, 2 in fm mode (pin 3 and pin 4) the gains of dac1 and dac2 have a range of 0.69 v (pdo) to 2.16 v (pdo) . v (pdo) is the pll tuning voltage output. this range is divided into 256 steps. so one step is approximately (2.16 - 0.46) v (pdo) / 255 = 0.005764 v (pdo) . the gain of dac1 can be controlled by the bits 36 to 43 (g-2 0 to g-2 7 ) and the gain of dac2 by the bits 0 to 7 (g- 2 0 to g-2 7 ) as following: offset = 31 (intermediate position) the offset of dac1 and dac2 has a range of 0.56 v to -0.59 v. this range is divided into 64 steps. so one step is approximately 1.15 v/ 63 = 18.25 mv. the offset dac1 can be controlled by the bits 44 to 49 (o-2 0 to o-2 5 ) and the offset of dac2 by the bits 8 to 13 (o-2 0 to o-2 5 ) as following: gain = 53 (intermediate position) gain dac1 approximately b43 b42 b41 b40 b39 b38 b37 b36 decimal gain gain dac2 approximatelyb7b6b5b4b3b2b1b0 decimal gain 0.69 v (pdo) 00000000 0 0.69576 v (pdo) 00000001 1 0.70153 v (pdo) 00000010 2 0.70729 v (pdo) 00000011 3 ... ... ... ... ... ... ... ... ... ... 0.99549 v (pdo) 00110101 53 ... ... ... ... ... ... ... ... ... ... 2.14847 v (pdo) 11111101 253 2.15424 v (pdo) 11111110 254 2.16 v (pdo) 11111111 255 offset dac1 approximately b49 b48 b47 b46 b45 b44 decimal gain offset dac2 approximately b13 b12 b11 b10 b9 b8 decimal gain 0.56 v 000000 0 0.5417 v000001 1 0.5235 v000010 2 0.5052 v000011 3 ... ... ... ... ... ... ... ... +0.0059 v 0 1 1 1 1 1 31 ... ... ... ... ... ... ... ... 0.5535 v111101 61 -0.5717 v111110 62 -0.59 v 111111 63
7 U4256BM-r 4562b?audr?02/03 dac 1, 2 in am mode (pin 3 and pin 4) in am mode the dac input voltage v (pdo) is internal connected to 3 v. the gains of dac1 and dac2 have a range of 0.46 3 v to 3.03 3v. v (pdo) is the pll tuning volt- age output. this range is divided into 256 steps. so one step is approximately (3.03 - 0.46) v/255 = 0.01007 3 v. the gain of dac1 can be controlled by the bits 36 to 43 (g-2 0 to g-2 7 ) and the gain of dac2 by the bits 0 to 7 (g-2 0 to g-2 7 ) as following: offset = 31 (intermediate position) remark: v (pdo) is 3 v in am mode. the offset of dac1 and dac2 has a range of +1.46 v to -1.49 v. this range is divided into 64 steps. so one step is approximately 2.95 v/ 63 = 46.8 mv. the offset dac1 can be controlled by the bits 44 to 49 (o-2 0 to o-2 5 ) and the offset of dac2 by the bits 8 to 13 (o-2 0 to o-2 5 ) as following: gain = 53 (intermediate position) gain dac1 approximately b43 b42 b41 b40 b39 b38 b37 b36 decimal gain gain dac2 approximatelyb7b6b5b4b3b2b1b0 decimal gain 0.4607 3v00000000 0 0.4710 3v00000001 1 0.4812 3v00000010 2 0.4915 3v00000011 3 ... ... ... ... ... ... ... ... ... ... 1.0029 3v00110101 53 ... ... ... ... ... ... ... ... ... ... 3.0097 3v11111101 253 3.0196 3v11111110 254 3.0296 3v11111111 255 offset dac1 approximately b49 b48 b47 b46 b45 b44 decimal gain offset dac2 approximately b13 b12 b11 b10 b9 b8 decimal gain 1.4606 v000000 0 1.4138 v000001 1 1.3665 v000010 2 1.3196 v000011 3 ... ... ... ... ... ... ... ... -0.0079 v011111 31 ... ... ... ... ... ... ... ... -1.3975 v111101 61 -1.4447 v111110 62 -1.4917 v111111 63
8 U4256BM-r 4562b?audr?02/03 dac3 (pin 5) the dac3 output voltage can be controlled by the bits p-2 0 to p-2 2 (bits 66 to 68) as following: figure 8. internal components at dac3 en, data, clk (pin 16-18) all functions can be controlled via a 3-wi re bus consisting of enable, data and clock. the bus is designed for microcontrollers which operate with 3 v supply voltage. details of the data transfer protocol are shown in the table ?3-wire bus description?. figure 9. internal components at en, data, clk dac3 offset approximately b68 b67 b66 0.55 v 0 0 0 1.25 v 0 0 1 1.90 v 0 1 0 2.60 v 0 1 1 3.30 v 1 0 0 4.10 v 1 0 1 4.80 v 1 1 0 5.45 v 1 1 1 vs dac3 v 5 en data clk
9 U4256BM-r 4562b?audr?02/03 swo1, 2, 3 and 4 (pin 7-10) all switching outputs are ?open drain? and can be set and reset by software control. details are described in the data transfer protocol. the switching output swo1 to swo4 can be controlled as following (bits 30 to 33): x = 0 to 3 figure 10. internal components at swo1, 2, 3 and 4 oscin, oscout (pin 12 and pin 13) a crystal resonator (up to 15 mhz) is connected between oscin and oscout in order to generate the reference frequency. by using the U4256BM- r in connection with u4255bm the crystal frequency must be 10.25 mhz. the complete application circuit is shown in figure 15. if a reference is available, it can be applied at oscin. the minimum voltage should be 100 mvrms. in this case, pin oscout has to be open. the tuning capacity for the crystal oscillator has a range of 0.5 pf to 71.5 pf. the values are coded binary. the tuning can be controlled by the bits 78 to 85 as following: switch output b30 + x swox = on (switch to gnd) 0 swox = off 1 swo1 swo2 swo3 swo4 i b85 = 1 [pf] b85 = 0 [pf] b84 b83 b82 b81 b80 b79 b78 0 8.0 1111111 0.5 8.5 1111110 1.0 9.0 1111101 1.5 19.5 1111100 ... ... ... ... ... ... ... ... ... 63.0 71.0 0000000 63.5 71.5 0000000
10 U4256BM-r 4562b?audr?02/03 figure 11. internal components at oscin and oscout figure 12. internal connection of tuning capacity for crystal oscillator v 5 oscin oscout v 5 32p 16p 0.5 p b78 0.5 p 16p 32p b84 b85 cx1 cx2 inv
11 U4256BM-r 4562b?audr?02/03 application information figure 13. fmoscin sensitivity 3-wire bus description the register settings of U4256BM-r are programmed by a 3-wire bus protocol. the bus protocol consists of separate commands. a defined number of bits is transmitted sequentially during each command. one command is used to program all the bits of one register. the different registers available (see table data transfer) are addressed by the length of the command (num- ber of transmitted bits) and by two address bits, that are unique to each register of a given length. 16-bit registers are programmed by 16-bit commands and 24-bit registers are programmed by 24-bit commands. each bus command starts with a rising edge on the enable line (en) and ends with a falling edge on en. en has to be kept high during the bus command. the sequence of transmitted bits during one command starts with the lsb of the first byte and ends with the msb of the last byte of the register addressed. to transmit one bit (0/1) data has to be set to the appropriate value (low/high) and a low to high transition has to be performed on the clock line (clk) while data is valid. the data is evaluated at the rising edges of clk. the number of low to high transitions on clk during the high period of en is used to determine the length of the command. the bus protocol and the register addressing of U4256BM-r are compatible to the addressing used in u4255bm and t4258. that means U4256BM-r and u4255bm (or t4258) can be operated on the same 3-wire bus as shown in the application circuit. 0 50 100 150 0 20 40 60 80 100 120 140 160 frequency (mhz) vi (mv rms on 50 )
12 U4256BM-r 4562b?audr?02/03 figure 14. 3-wire bus timing diagram figure 15. 3-wire pulse diagram t r t f t s t hen t r t s t hda t f t h t l enable data clock t r t f v high v low v high v low v high v low 12 24-bit command 16-bit command data clk lsb lsb msb msb byte 1 byte 2 en en clk data lsb lsb msb msb byte 3 byte 2 msb lsb byte 1 en e.g. r-divider 0 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 2 13 ipd p-2 1 r-divider addr. p-2 0 p-2 2 status 0 oscb 2 14 2 15 dac3
13 U4256BM-r 4562b?audr?02/03 data transfer table 1. control registers a msb byte 3 lsb msb byte 2 lsb msb byte 1 lsb addr. status 0 dac3 r-divider 00 ipd oscb 0=on, 1=off p-2 2 p-2 1 p-2 0 2 15 2 14 2 13 2 12 2 10 2 11 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b71 b70 b69 b68 b67 b66 b65 b64 b63 b62 b61 b60 b59 b58 b57 b56 b55 b54 b53 b52 b51 b50 b msb byte 3 lsb msb byte 2 lsb msb byte 1 lsb addr. status 1 n-divider 010 am=1 fm=0 dac swo4 0=on, 1=off swo3 0=on, 1=off swo2 0=on, 1=off swo1 0=on, 1=off 2 15 2 14 2 13 2 12 2 10 2 11 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b35 b34 b33 b32 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 c msb byte 2 lsb msb byte 1 lsb addr. dac1 offset dac1 gain 00o-2 5 o-2 4 o-2 3 o-2 2 o-2 1 o-2 0 g-2 7 g-2 6 g-2 7 g-2 5 g-2 4 g-2 3 g-2 2 g-2 0 b49 b48 b47 b46 b45 b44 b43 b42 b41 b40 b39 b38 b37 b36 d msb byte 2 lsb msb byte 1 lsb addr. dac2 offset dac2 gain 01o-2 5 o-2 4 o-2 3 o-2 2 o-2 1 o-2 0 g-2 7 g-2 6 g-2 7 g-2 5 g-2 4 g-2 3 g-2 2 g-2 0 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 e msb byte 2 lsb msb byte 1 lsb addr. oscillator tuning function not used 108pf32pf16pf8pf4pf2pf1pf0.5pfxxxxxx b85 b84 b83 b82 b81 b80 b79 b78 b77 b76 b75 b74 b73 b72 absolute maximum ratings parameters symbol value unit analog supply voltage pin 6 v s 8 to 12 v input voltage bus pins 16, 17 and 18 v i -0.3 to +5.3 v output current switches pins 7, 8, 9 and 10 (see figure 10) i o -1 to +5 ma drain voltage switches pins 7, 8, 9 and 10 v od 15 v ambient temperature range t amb -40 to +85 c storage temperature range t stg -40 to +125 c junction temperature t j 125 c electrostatic handling m.m. v esd 300 v
14 U4256BM-r 4562b?audr?02/03 thermal resistance parameters symbol value unit junction ambient, when soldering to pcb r thja 140 k/w operating range all voltages are referred to gnd (pin 11) parameters symbol min. typ. max. unit supply voltage range pin 6 v s 88.512v ambient temperature t amb -40 +85 c input frequency fmoscin pin 19 f in 70 160 mhz programmable n, r divider sf 2 65535 crystal reference oscillator pins 12 and 13 fxtal 0.1 15 mhz electrical characteristics test conditions (unless otherwise specified): v s = 8.5 v, t amb = 25c. no. parameters test conditions pin symbol min. typ. max. unit type* 1 supply voltage 1.1 analog supply voltage 6 v s 88.512va 2 supply current 2.1 analog supply current 6 i s 51025maa 3oscin 3.1 input voltage f = 0.1 to 15 mhz 13 osc 100 mv rms b 4 osc buffer (mx2lo) 4.1 output ac voltage at pin15: 47 pf and 1k 15 v mx2lo 80 120 200 mv pp b 4.2 output dc voltage 15 v mx2lo 1.8 2.0 2.2 v a 5fmoscin 5.1 input voltage f = 70 to 120 mhz f = 120 to 160 mhz 19 fmosc fmosc 40 150 mv rms mv rms b 6 pulsed current output pd 6.1 output current bit 71, 70 = ?00? pd = 2.5 v 2 ipd 20 25 30 a a 6.2 output current bit 71, 70 = ?01? pd = 2.5 v 2 ipd 80 100 120 a a 6.3 output current bit 71, 70 = ?10? pd = 2.5 v 2 ipd 400 500 600 a a 6.4 output current bit 71, 70 = ?11? pd = 2.5 v 2 ipd 1500 2000 2400 a a 6.5 leakage current pd = 2.5 v 2 ipdl 20 na a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
15 U4256BM-r 4562b?audr?02/03 7pdo 7.1 saturation voltage high 3, 4 8.0 8.5 v a 7.2 saturation voltage low 3, 4 0 0.4 v a 8 swo1, swo2, swo3, swo4 (open drain) 8.1 output leakage current high pin 7,8,9,10 over r against 8.5 v 7, 8, 9, 10 i swoh 100 na a 8.2 output voltage low i = 1 ma 7, 8, 9, 10 v swol 100 400 mv a 9 dac1, dac2 9.1 output current 3, 4 i dac1, 2 1mac 9.2 output voltage 3, 4 v dac1, 2 0.3 v s -0.6 v a 9.3 maximum offset range (fm) offset = 0, gain = 53 3, 4 0.45 0.56 0.65 v a 9.4 minimum offset range (fm) offset = 63, gain = 53 3, 4 -0.45 -0.57 -0.65 v a 9.5 maximum gain range (fm) gain = 255, offset = 31 3, 4 0.63 0.69 0.75 a 9.6 minimum gain range (fm) gain = 0, offset = 31 3, 4 2.1 2.16 2.23 a 10 dac3 10.1 output current 5 i dac3 1mac 10.2 output voltage bit 68-66: 000 5 v dac3 0.4 0.55 0.7 v a 10.3 output voltage bit 68-66: 001 5 v dac3 1.1 1.25 1.4 v a 10.4 output voltage bit 68-66: 010 5 v dac3 1.8 1.90 2.1 v a 10.5 output voltage bit 68-66: 011 5 v dac3 2.4 2.60 2.8 v a 10.6 output voltage bit 68-66: 100 5 v dac3 3.2 3.30 3.5 v a 10.7 output voltage bit 68-66: 101 5 v dac3 3.8 4.10 4.3 v a 10.8 output voltage bit 68-66: 110 5 v dac3 4.5 4.80 5.0 v a 10.9 output voltage bit 68-66: 111 5 v dac3 5.2 5.45 5.7 v a 11 3-wire bus, enable, data, clock 11.1 input voltage high low 16-18 v bush v busl 2.7 -0.3 5.3 0.8 v v a 11.2 clock frequency 17 1.0 mhz a 11.3 period of clk high low 17 t h t l 250 250 ns ns d 11.4 rise time en, data, clk 16-18 t r 400 ns d 11.5 fall time en, data, clk 16-18 t f 100 ns d electrical characteristics (continued) test conditions (unless otherwise specified): v s = 8.5 v, t amb = 25c. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
16 U4256BM-r 4562b?audr?02/03 figure 16. application circuit 11.6 set-up time 16-18 t s 100 ns d 11.7 hold time en 18 t hen 250 ns d 11.8 hold time data 16 t hda 0nsd electrical characteristics (continued) test conditions (unless otherwise specified): v s = 8.5 v, t amb = 25c. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 20 123 4 56 7 8 19 18 17 16 15 14 13 9 10 12 11 c 1 10 pf r 2 600 fm vco r 4 8.2 k c 6 330 pf c 7 10 nf c 8 47 pf r 5 5.1 k 10.25 mhz c 9 *) c 12 100 nf en clk data gnd c 5 100 nf c 4 100 mf r 3 100 c 16 10 nf c 15 10 nf 10 nf c 14 dac1 dac2 dac3 swo1 swo2 vs 8 ... 12 v swo3 swo4 f osc *) *) depends on crystal bus osc logic dac's switches v tune
17 U4256BM-r 4562b?audr?02/03 figure 17. application board schematic 12 13 u4255bm 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 18p c203 22u c131c132 f131 bb804 1 2 3 4 5 6 7 8 9 10 U4256BM 20 19 18 17 16 15 14 13 12 11 c314 10n f102 c112 10u c113 100n swo1 dac3 swo2 swo3 swo4 int if2out data clk en gnd mpx adjac meter c310 f302 multip dev c208 c205 c202 f201 q151 r407 10 r106 10 r152 10 c312 10n 1n c309 r303 1k 220n c207 r305 1k5 x301 r304 1k3 r34 27 kr201 r313 390 c111 470n c in f201 100p c307 10n c209 r29 10 c308 100n vs (+8,5v...10,5v) r311 2k2 r105 100 r115 1k t102 bc858 c109 c108 r102 68k c110 4n7 r121 68k r122 68k c56 10p c104 10n r112 47k l102 r104 470 c117 c107 2u2 c106 27p f101 bb804 d101 c103 c102 10n c311 100n r103 1k 3p9 d103 s391d 10n d302 l301 4u7 l303 2m2 l302 100uh c306 c319 12p 6p8 bc 858c c316 r308 2k2 220n r307 47 c315 220n c302 10n r306 470k r151 8k2 c152 330p c134 1n c151 10n c158 10n c159 c157 10n 10n c154 c153 c155 c156 10n 10,25mhz 12p* 12p* 100n c114 220n c133 6p8 47p 22p r131 5k6 kf302 kr202 220n 220n c204 c206 r111 200k 1u 10n 10u 470n c116 c115 100n 100n 10n t301 t302 bc848 t111 j109 t101 bfr93a ant fm 75 ohm s391d d301 s391d c201 100n d131 d102 bb804 1n 6p8 *depends on q151
18 U4256BM-r 4562b?audr?02/03 package information ordering information extended type number package remarks U4256BM-rfs sso20 tube U4256BM-rsg3 sso20 taped and reeled technical drawings according to din specifications package sso20 dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.1 5 20 11 110
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